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IDT5T93GL06 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II
INDUSTRIAL TEMPERATURE RANGE
2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFERTM II
FEATURES:
* * * * * * * * * * * *
IDT5T93GL06
DESCRIPTION:
Guaranteed Low Skew < 25ps (max) Very low duty cycle distortion < 100ps (max) High speed propagation delay < 2ns (max) Up to 800MHz operation Glitchless input clock switching up to 650MHz Selectable inputs Hot insertable and over-voltage tolerant inputs 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input interface Selectable differential inputs to six LVDS outputs Power-down mode 2.5V VDD Available in TQFP and VFQFPN packages
APPLICATIONS:
* Clock distribution
The IDT5T93GL06 2.5V differential clock buffer is a user-selectable differential input to six LVDS outputs . The fanout from a differential input to six LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The IDT5T93GL06 can act as a translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for a glitchless change-over from a primary clock source to a secondary clock source up to 650MHz. Selectable inputs are controlled by SEL. During the switchover, the output will disable low for up to three clock cycles of the previously-selected input clock. The outputs will remain low for up to three clock cycles of the newlyselected clock, after which the outputs will start from the newly-selected input. A FSEL pin has been implemented to control the switchover in cases where a clock source is absent or is driven to DC levels below the minimum specifications. The IDT5T93GL06 outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise.
FUNCTIONAL BLOCK DIAGRAM
GL G
OUTPUT CONTROL
Q1 Q1
PD
OUTPUT CONTROL
Q2 Q2
A1 A1
1
OUTPUT CONTROL Q3 Q3
A2 A2
0
OUTPUT CONTROL
Q4 Q4
SEL FSEL
OUTPUT CONTROL
Q5 Q5
OUTPUT CONTROL
Q6 Q6
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
OCTOBER 2003
DSC-6183/7
(c) 2003 Integrated Device Technology, Inc.
IDT5T93GL06 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
Q6
28 27 26 25 24 23 22 G VDD Q1 Q1 VDD A1 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 GND 21 20 19 18 17 16 15 PD VDD Q4 Q4 VDD A2 A2
VDD
VFQFPN
TOP VIEW
2
VDD
GL
Q2
Q2
Q3
Q3
FSEL
SEL
VDD
Q6
Q5
Q5
IDT5T93GL06 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATIONS (CONTINUED)
32 31 30 29 28 27 26 25 G VDD GND Q1 Q1 GND A1 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 PD VDD GND Q4 Q4 GND A2 A2
VDD
GND GND
TQFP(1) TOP VIEW
NOTE: 1. 1m/s of airflow is required for TQFP in order to sustain normal operation.
3
VDD
GL
Q2
Q2
Q3
Q3
FSEL
SEL
VDD
Q6
Q6
Q5
Q5
IDT5T93GL06 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDD VI VO TSTG TJ Input Voltage Output Voltage(2) Storage Temperature Junction Temperature Description Power Supply Voltage Max -0.5 to +3.6 -0.5 to +3.6 -0.5 to VDD +0.5 -65 to +150 150 Unit V V V C C
CAPACITANCE(1) (TA = +25C, F = 1.0MHz)
Symbol CIN Parameter Input Capacitance Min Typ. Max. 3 Unit pF
--
--
NOTE: 1. This parameter is measured at characterization but not tested
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Not to exceed 3.6V.
RECOMMENDED OPERATING RANGE
Symbol TA VDD Description Ambient Operating Temperature Internal Power Supply Voltage Min. -40 2.3 Typ. +25 2.5 Max. +85 2.7 Unit C V
PIN DESCRIPTION
Symbol A[1:2] A[1:2] I/O I I Type Adjustable(1,4) Adjustable(1,4) Description Clock input. A[1:2] is the "true" side of the differential clock input. Complementary clock inputs. A[1:2] is the complementary side of A[1:2]. For LVTTL single-ended operation, A[1:2] should be set to the desired toggle voltage for A[1:2]: 3.3V LVTTL VREF = 1650mV 2.5V LVTTL VREF = 1250mV Gate control for differential outputs Q1 and Q1 through Q6 and Q6. When G is LOW, the differential outputs are active. When G is HIGH, the differential outputs are asynchronously driven to the level designated by GL(2). Specifies output disable level. If HIGH, "true" outputs disable HIGH and "complementary" outputs disable LOW. If LOW, "true" outputs disable LOW and "complementary" outputs disable HIGH. Clock outputs Complementary clock outputs Reference clock select. When LOW, selects A2 and A2. When HIGH, selects A1 and A1. Power-down control. Shuts off entire chip. If LOW, the device goes into low power mode. Inputs and outputs are disabled. Both "true" and "complementary" outputs will pull to VDD. Set HIGH for normal operation.(3) Forces selection of clock input. If HIGH, FSEL forces select to the input designated by SEL. Set LOW for normal operation. Power supply for the device core and inputs Ground
G GL Qn Qn SEL PD FSEL VDD GND
I I O O I I I
LVTTL LVTTL LVDS LVDS LVTTL LVTTL LVTTL PWR PWR
NOTES: 1. Inputs are capable of translating the following interface standards: Single-ended 3.3V and 2.5V LVTTL levels Differential HSTL and eHSTL levels Differential LVEPECL (2.5V) and LVPECL (3.3V) levels Differential LVDS levels Differential CML levels 2. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry. 3. It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes powerup after asserting PD. 4. The user must take precautions with any differential input interface standard being used in order to prevent instability when there is no input signal.
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IDT5T93GL06 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING RANGE FOR LVTTL(1)
Symbol Parameter Input Characteristics IIH Input HIGH Current IIL Input LOW Current VIK Clamp Diode Voltage VIN DC Input Voltage VIH DC Input HIGH VIL DC Input LOW VTHI DC Input Threshold Crossing Voltage Single-Ended Reference Voltage(3) VREF Test Conditions VDD = 2.7V VDD = 2.7V VDD = 2.3V, IIN = -18mA Min. -- -- -- - 0.3 1.7 -- -- -- Typ.(2) -- -- - 0.7 Max 5 5 - 1.2 +3.6 -- 0.7 -- -- Unit A V V V V V V
3.3V LVTTL 2.5V LVTTL
VDD/2 1.65 1.25
NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. Typical values are at VDD = 2.5V, +25C ambient. 3. For A[1:2] single-ended operation, A[1:2] is tied to a DC reference voltage.
DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING RANGE FOR DIFFERENTIAL INPUTS(1)
Symbol Parameter Input Characteristics IIH Input HIGH Current IIL Input LOW Current VIK Clamp Diode Voltage VIN DC Input Voltage VDIF DC Differential Voltage(2) VCM DC Common Mode Input Voltage(3) Test Conditions VDD = 2.7V VDD = 2.7V VDD = 2.3V, IIN = -18mA Min. -- -- -- - 0.3 0.1 0.05 Typ.(4) -- -- - 0.7 Max 5 5 - 1.2 +3.6 -- VDD Unit A V V V V
NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state. 3. VCM specifies the maximum allowable range of (VTR + VCP) /2. 4. Typical values are at VDD = 2.5V, +25C ambient.
DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING RANGE FOR LVDS(1)
Symbol Parameter Output Characteristics VOT(+) Differential Output Voltage for the True Binary State VOT(-) Differential Output Voltage for the False Binary State VOT Change in VOT Between Complementary Output States VOS Output Common Mode Voltage (Offset Voltage) VOS Change in VOS Between Complementary Output States IOS Outputs Short Circuit Current IOSD Differential Outputs Short Circuit Current
NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. Typical values are at VDD = 2.5V, +25C ambient.
Test Conditions
Min. 247 247 -- 1.125 -- -- --
Typ.(2) -- -- -- 1.2 -- 12 6
Max 454 454 50 1.375 50 24 12
Unit mV mV mV V mV mA mA
VOUT + and VOUT - = 0V VOUT + = VOUT -
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IDT5T93GL06 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II
INDUSTRIAL TEMPERATURE RANGE
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR HSTL
Symbol VDIF VX DH VTHI tR, tF Parameter Input Signal Swing(1) Differential Input Signal Crossing Point Duty Cycle Input Timing Measurement Reference Level Input Signal Edge Rate(4)
(3) (2)
Value 1 750 50 Crossing Point 2
Units V mV % V V/ns
NOTES: 1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions. 2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR eHSTL
Symbol VDIF VX DH VTHI tR, tF Parameter Input Signal Swing(1) Differential Input Signal Crossing Point Duty Cycle Input Timing Measurement Reference Level Input Signal Edge Rate(4)
(3) (2)
Value 1 900 50 Crossing Point 2
Units V mV % V V/ns
NOTES: 1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions. 2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR LVEPECL (2.5V) AND LVPECL (3.3V)
Symbol VDIF VX DH VTHI tR, tF Parameter Input Signal Swing(1) Differential Input Signal Crossing Point Duty Cycle Input Timing Measurement Reference Level(3) Input Signal Edge Rate
(4) (2)
Value 732 LVEPECL LVPECL 1082 1880 50 Crossing Point 2
Units mV mV % V V/ns
NOTES: 1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions. 2. 1082mV LVEPECL (2.5V) and 1880mV LVPECL (3.3V) crossing point levels are specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
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IDT5T93GL06 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II
INDUSTRIAL TEMPERATURE RANGE
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR LVDS
Symbol VDIF VX DH VTHI tR, tF Parameter Input Signal Swing(1) Differential Input Signal Crossing Point Duty Cycle Input Timing Measurement Reference Level(3) Input Signal Edge Rate(4)
(2)
Value 400 1.2 50 Crossing Point 2
Units mV V % V V/ns
NOTES: 1. The 400mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions. 2. A 1.2V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
AC DIFFERENTIAL INPUT SPECIFICATIONS(1)
Symbol VDIF VIX VCM VIN Parameter AC Differential Voltage
(2)
Min. 0.1 0.05 0.05 - 0.3
Typ. -- -- --
Max 3.6 VDD VDD +3.6
Unit V V V V
Differential Input Crosspoint Voltage Common Mode Input Voltage Range(3) Input Voltage
NOTES: 1. The output will not change state until the inputs have crossed and the minimum differential voltage defined by VDIF has been met or exceeded. 2. VDIF specifies the minimum input voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. The AC differential voltage must be achieved to guarantee switching to a new state. 3. VCM specifies the maximum allowable range of (VTR + VCP) /2.
POWER SUPPLY CHARACTERISTICS FOR LVDS OUTPUTS(1)
Symbol IDDQ ITOT IPD Parameter Quiescent VDD Power Supply Current Total Power VDD Supply Current Total Power Down Supply Current Test Conditions VDD = Max., All Input Clocks = LOW(2) Outputs enabled VDD = 2.7V., FREFERENCE CLOCK = 800MHz PD = LOW Typ. -- -- -- Max 250 240 5 Unit mA mA mA
NOTES: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case conditions. 2. The true input is held LOW and the complementary input is held HIGH.
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IDT5T93GL06 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE(1,5)
Symbol Skew Parameters tSK(O) tSK(P) tSK(PP) Propagation Delay tPLH tPHL Parameter Same Device Output Pin-to-Pin Skew(2) Pulse Skew(3) Part-to-Part Skew(4) Propagation Delay A, A Crosspoint to Qn, Qn Crosspoint Min. -- -- -- -- -- -- -- -- -- Typ. -- -- -- 1.5 -- -- -- -- -- Max 25 100 300 2 800 3.5 3.5 100 100 Unit ps ps ps ns MHz ns ns S S
fO Frequency Range(6) Output Gate Enable/Disable Delay tPGE tPGD Power Down Timing tPWRDN tPWRUP Output Gate Enable Crossing VTHI to Qn/Qn Crosspoint Output Gate Disable Crossing VTHI to Qn/Qn Crosspoint Driven to GL Designated Level PD Crossing VTHI to Qn = VDD, Qn = VDD Output Gate Disable Crossing VTHI to Qn/Qn Driven to GL Designated Level
NOTES: 1. AC propagation measurements should not be taken within the first 100 cycles of startup. 2. Skew measured between crosspoints of all differential output pairs under identical input and output interfaces, transitions and load conditions on any one device. 3. Skew measured is the difference between propagation delay times tPHL and tPLH of any single differential output pair under identical input and output interfaces, transitions and load conditions on any one device. 4. Skew measured is the magnitude of the difference in propagation times between any single differential output pair of two devices, given identical transitions and load conditions at identical VDD levels and temperature. 5. All parameters are tested with a 50% input duty cycle. 6. Guaranteed by design but not production tested.
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IDT5T93GL06 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II
INDUSTRIAL TEMPERATURE RANGE
DIFFERENTIAL AC TIMING WAVEFORMS
1/fo
A[1:2] - A[1:2]
+ VDIF VDIF = 0 - VDIF tPLH tPHL + VDIF VDIF = 0 - VDIF tSK(O) + VDIF VDIF = 0 - VDIF
Qn - Qn tSK(O)
Qm - Qm
Output Propagation and Skew Waveforms
NOTES: 1. Pulse skew is calculated using the following expression: tSK(P) = | tPHL - tPLH | Note that the tPHL and tPLH shown above are not valid measurements for this calculation because they are not taken from the same pulse. 2. AC propagation measurements should not be taken within the first 100 cycles of startup.
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IDT5T93GL06 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II
INDUSTRIAL TEMPERATURE RANGE
A[1:2] - A[1:2]
+ VDIF VDIF = 0 - VDIF VIH VTHI VIL tPLH VIH VTHI VIL tPGD tPGE + VDIF VDIF = 0 - VDIF
GL
G
Qn - Qn
Differential Gate Disable/Enable Showing Runt Pulse Generation
NOTE: 1. As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time the G signal to avoid this problem.
A1 - A1
+ VDIF VDIF = 0 - VDIF + VDIF VDIF = 0 - VDIF VIH VTHI VIL + VDIF VDIF = 0 - VDIF
A2 - A2
SEL
Qn - Qn
Glitchless Output Operation with Switching Input Clock Selection
NOTES: 1. When SEL changes, the output clock goes LOW on the falling edge of the output clock up to three cycles later. The output then stays LOW for up to three clock cycles of the new input clock. After this, the output starts with the rising edge of the new input clock. 2. AC propagation measurements should not be taken within the first 100 cycles of startup.
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IDT5T93GL06 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II
INDUSTRIAL TEMPERATURE RANGE
+VDIF VDIF=0 -VDIF +VDIF VDIF=0 -VDIF VIH VTHI VIL VIH VTHI VIL
A1 - A1
A2 - A2
SEL
FSEL
Qn - Qn
+VDIF VDIF=0 -VDIF
FSEL Operation for When Current Clock Dies
NOTES: 1. When the differential on the selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state. When this happens, the SEL pin should be toggled and FSEL asserted in order to force selection of the new input clock. The output clock will start up after a number of cycles of the newly-selected input clock. 2. The FSEL pin should stay asserted until the problem with the dead clock can be fixed in the system. 3. It is recommended that the FSEL be tied HIGH for systems that use only one input. If this is not possible, the user must guarantee that the unused input have a differential greater than or equal to the minimum DC differential specified in the datasheet.
A1 - A1
+VDIF VDIF=0 -VDIF +VDIF VDIF=0 -VDIF VIH VTHI VIL VIH VTHI VIL
A2 - A2
SEL
FSEL
Qn - Qn
+VDIF VDIF=0 -VDIF
FSEL Operation for When Opposite Clock Dies
NOTES: 1. When the differential on the non-selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state. When this happens, the FSEL pin should be asserted in order to force selection of the new input clock. The output clock will start up after a number of cycles of the newly-selected input clock. 2. The FSEL pin should stay asserted until the problem with the dead clock can be fixed in the system. 3. It is recommended that the FSEL be tied HIGH for systems that use only one input. If this is not possible, the user must guarantee that the unused input have a differential greater than or equal to the minimum DC differential specified in the datasheet.
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IDT5T93GL06 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II
INDUSTRIAL TEMPERATURE RANGE
+VDIF VDIF=0 -VDIF +VDIF VDIF=0 -VDIF VIH VTHI VIL VIH VTHI VIL
A1 - A1
A2 - A2
SEL
FSEL
Qn - Qn
+VDIF VDIF=0 -VDIF
FSEL Operation to Protect Against When Opposite Clock Dies
NOTES: 1. If the user holds FSEL HIGH, the output will not be affected by the deselected input clock. 2. The output will immediately be driven to LOW once FSEL is asserted. This may cause glitching on the output. The output will restart with the input clock selected by the SEL pin. 3. If the user decides to switch input clocks, the user must de-assert FSEL, then assert FSEL after toggling the SEL input pin. The output will be driven LOW and will restart with the input clock selected by the SEL pin.
A1 - A1
+VDIF VDIF=0 -VDIF +VDIF VDIF=0 -VDIF VIH VTHI VIL VIH VTHI VIL
A2 - A2
FSEL
SEL
Qn - Qn
+VDIF VDIF=0 -VDIF
Selection of Input While Protecting Against When Opposite Clock Dies
NOTES: 1. If the user holds FSEL HIGH, the output will not be affected by the deselected input clock. 2. The output will immediately be driven to LOW once FSEL is asserted. This may cause glitching on the output. The output will restart with the input clock selected by the SEL pin. 3. If the user decides to switch input clocks, the user must de-assert FSEL, then assert FSEL after toggling the SEL input pin. The output will be driven LOW and will restart with the input clock selected by the SEL pin.
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IDT5T93GL06 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II
INDUSTRIAL TEMPERATURE RANGE
A1 - A1
+VDIF VDIF=0 -VDIF +VDIF VDIF=0 -VDIF VIH VTHI VIL VIH VTHI VIL +VDIF VDIF=0 -VDIF
A2 - A2
G
PD
Qn - Qn
Power Down Timing
NOTES: 1. It is recommended that outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power-up after asserting PD. 2. The POWER DOWN TIMING diagram assumes that GL is HIGH. 3. It should be noted that during power-down mode, the outputs are both pulled to VDD. In the POWER DOWN TIMING diagram this is shown when Qn - Qn goes to VDIF = 0.
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IDT5T93GL06 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND CONDITIONS
VIN
~50 Transmission Line VDD/2
A
Pulse Generator
VIN ~50 Transmission Line A
D.U.T.
-VDD/2
Scope
50 50
Test Circuit for Differential Input
DIFFERENTIAL INPUT TEST CONDITIONS
Symbol VTHI VDD = 2.5V 0.2V Crossing of A and A Unit V
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IDT5T93GL06 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II
INDUSTRIAL TEMPERATURE RANGE
VDD
Pulse Generator
A A
Qn RL
D.U.T.
RL Qn
VOS
VOD
Test Circuit for DC Outputs and Power Down Tests
VDD/2
CL Z = 50
SCOPE
Pulse Generator
A A
Qn 50
D.U.T.
50 Qn Z = 50 CL -VDD/2
Test Circuit for Propagation, Skew, and Gate Enable/Disable Timing
LVDS OUTPUT TEST CONDITION
Symbol CL RL VDD = 2.5V 0.2V 0(1) 8(1,2) 50 Unit pF
NOTES: 1. Specifications only apply to "Normal Operations" test condition. The TIA/EIA specification load is for reference only. 2. The scope inputs are assumed to have a 2pF load to ground. TIA/EIA - 644 specifies 5pF between the output pair. With CL = 8pF, this gives the test circuit appropriate 5pF equivalent load.
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IDT5T93GL06 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XXXXX Device Type XX Package X Process
I
-40C to +85C (Industrial)
PF NL
Thin Quad Flat Pack Thermally Enhanced Plastic Very Fine Pitch Quad Flat No Lead Package 2.5V LVDS 1:6 Glitchless Clock Buffer TerabufferTM II
5T93GL06
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for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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